The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of forming a shallow trench isolation (STI) by introducing a step of treating an oxide layer by nitrogen after the shallow trench is formed by etching.
A completed integrated circuit is generally constructed with thousands of metal oxide semiconductor (MOS) transistors. In order to avoid a circuit short between neighbored transistors, an isolation structure is employed for electrical isolating the transistors.
When the circuit integration is increased, size of the electric device must be scaled down. Hence, the isolation structure between the devices also must be scaled down in accordance with the devices, and thereby results in a difficult of forming the isolation structure. A variety of device isolation has been developed, wherein a shallow trench isolation (STI) technique is commonly used, and is currently applied in the integrated circuit process, especially in the sub-half micron integrated circuit process.
Referring o FIGS. 1 through 5, showing, a conventional process of making the shallow trench isolation structure. As shown in FIG. 1, a semiconductor substrate 10, typically a silicon substrate, is provided. A pad oxide layer 12, for example, a silicon oxide layer, is then formed on the semiconductor substrate 10 by heating in an oxygen-containing condition. After that, a silicon nitride layer 14 is then deposited on the pad oxide layer 12 by, for example, LPCVD or other deposition method. A photolithography process is then performed on the wafer.
Referring to FIG. 2, a layer of photoresist is then patterned to expose the silicon nitride layer 14 after the forming step of the silicon nitride 14. A predetermined mask pattern is then transferred to the layer of photoresist to form the photoresist layer 16. Thereafter, an etching process is then performed on the wafer.
Referring to FIG. 3, the formed photoresist layer 16 can be used as the mask during the etching process. The underlying silicon nitride layer 14, pad oxide layer 12 and substrate 10 are then etched sequentially by wet etching or dry etching. Therefore. a trench 20 is then formed on the substrate 10.
Referring to FIG. 4, while the trench 20 has a predetermined depth during the etching process, a liner oxide layer 18 is then conformal formed on the surface of the etched trench 20. The photoresist layer 16 is then removed. Thereafter, a silicon oxide layer 22 is then formed to fill the trench 20 by, for example, CVD or other deposition method. A polishing process is then preformed on the wafer.
Referring o FIG. 5, a CMP process is then applied to remove the silicon nitride layer 14, oxide layer 22, and pad oxide layer 12, exceed the trench 20, and leave the layers located within the trench 20. Since the pad oxide layer is exposed, therefore a bird""s break is easily formed in the subsequent processes and the exposed surface of the pad oxide layer is then enlarged, especially in the etching process for patterning the shallow trench.
As described above, a bird""s break is easily formed on the pad oxide layer and the exposed surface of the pad oxide layer is then enlarged during the etching process for patterning. This bird""s break will occupy the active area result in the difficulty to reduce the size of device.
Moreover, although an improved method is applied to inhibit the forming of the bird""s break by etching back the pad oxide layer. However, it is difficult to control the deposition of silicon. Therefore, voids are formed and the electric property of the device is then affected. Accordingly, it is necessary to introduce an effective method to solve this bird""s break problem.
Since a bird""s break is easily formed on the pad oxide layer and the exposed surface of the pad oxide layer is then enlarged during the etching process for patterning in the convention method of forming the shallow trench isolation.
It is therefore one aspect of the present invention to provide a method of forming a shallow trench isolation. The present invention comprises the steps of forming a trench on a substrate, wherein the substrate having a stacked structure composed of a pad oxide layer and a silicon nitride layer; forming a liner oxide layer on a sidewall of the trench; and performing a nitrogen treatment to transfer the pad oxide layer into silicon oxynitride layer.
It is another aspect of the present invention to provide a method of forming a shallow trench isolation. The present invention comprises the steps of forming a trench on a substrate, wherein the substrate having a stacked structure composed of a pad oxide layer and a silicon nitride layer; forming a liner oxide layer on a sidewall of the trench; performing a nitrogen treatment to transfer the pad oxide layer into silicon oxynitride layer; and forming a silicon oxide layer to fill the trench.
It is another aspect of the present invention to provide a method of forming a shallow trench isolation. The present invention comprises the steps of forming a pad oxide layer and a silicon nitride layer sequentially on a semiconductor substrate; performing a nitrogen treatment to transfer the pad oxide layer into silicon oxynitride layer; performing a photolithographic step to form a trench on the semiconductor substrate; forming a liner oxide layer on a sidewall of the trench; forming a silicon oxide layer to fill the trench; and performing a polishing step.
As described above, the present invention discloses a method of forming the shallow trench isolation by introducing a nitrogen treatment after the step of forming the trench so that the exposed pad oxide layer located on the upper portion of the trench is transferred into silicon oxynitride layer. Therefore, the method of the present invention avoids the formation of the bird""s break and electric influence of the device. Accordingly, the scale down requirement of the future device is satisfied according to the method of the present invention.
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
FIGS. 1 to 5 are schematic drawings, showing a conventional process of forming a shallow trench isolation; and
FIGS. 6 to 11 are schematic drawings, showing a method of forming a shallow trench isolation according to the present invention.